The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device which can reduce gate-induced drain leakage (GIDL) and parasitic capacitance and a method for manufacturing the same.
As the integration level of a semiconductor device increases, the sizes of the patterns formed in a semiconductor integrated circuit decrease. In conformity with this trend, various structures and process techniques for preventing the characteristics of a semiconductor device from being degraded have been developed and adopted.
For example, as a semiconductor device is highly integrated, the width of a gate decreases. Due to this, as a channel length decreases, a short channel effect, in which a threshold voltage abruptly decreases, results. In order to prevent the short channel effect, a lightly doped drain (LDD) region is formed. In this regard, in the case of a semiconductor device having a sub-100 nm level, since a channel length further decreases, it is difficult to prevent the short channel effect only through the formation of the LDD region. Accordingly, in order to obtain the threshold voltage (Vt) required in a highly integrated semiconductor device having a sub-100 nm level, a transistor structure having a recessed channel has been proposed in the art in place of a conventional transistor structure having a planar channel.
In the transistor structure having a recessed channel, the channel forming areas of an active region are recessed, and gates are formed in and over the recessed channel forming areas of the active region. In the transistor having the recessed channel, when compared to the conventional transistor having a planar channel, a channel length can be further increased in the same area, and thus, the short channel effect can be efficiently suppressed. Specifically, because the transistor having the recessed channel possesses a low junction field and a long channel length, the transistor can contribute to the increase in the margin of a semiconductor device.
However, in the transistor having the recessed channel, since the overlap area between a gate and an LDD region is increased when compared to the conventional transistor having a planar channel, a problem is caused in that gate-induced drain leakage (GIDL) increases.
FIG. 1 is a sectional view illustrating a transistor having a conventional recessed channel. Referring to FIG. 1, GIDL mainly occurs on the upper ends of the sidewalls of recesses. This is caused by the fact that the high doping concentration of an LDD region and the outward diffusion of a dopant from landing plugs act on the weak portions of a gate insulation layer (not shown) at the upper ends of the sidewalls of the recesses. The GIDL also occurs between passing gates and a device isolation structure, which serves as a factor for increasing leakage current, whereby the refresh characteristics of a semiconductor device can be deteriorated.
In FIG. 1, the reference numeral 108 designates junction areas including the LDD region, and 110 recess gates. Also, the reference character A designates the main occurrence positions of is GIDL, and B designates the occurrence position of GIDL attributable to the passing gates 112.
Further, in the transistor having the recessed channel, when compared to the conventional transistor having a planar channel, since parasitic capacitance increases between a gate and a bit line and between a gate and a storage node contact owing to structural issues, a problem is caused in that a sensing margin decreases relatively.
In the meanwhile, the problems caused by the increase in the GIDL and the increase in the parasitic capacitance can be solved by a method of increasing the thickness of a gate oxide layer on the sidewall of the recess using the directionality in oxidation. However, in this case, since an effective oxide thickness increases and the amount of current decreases, the method cannot be actually adopted.
Also, the problems caused by the increase in the GIDL and the increase in the parasitic capacitance can be solved by a method of decreasing the concentration of the landing plug. This method employs a principle that, as the outward diffusion of a dopant from the landing plug is suppressed, an electric field is decreased. Nevertheless, in this case, while GIDL can be suppressed, because a depletion width increases due to the decrease in the concentration on a junction surface, and due to this, junction leakage and resistance increase, the method cannot also be actually adopted.